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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\FPGA\TangNano-9K-example\hdmi\impl\gwsynthesis\hdmi.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>D:\FPGA\TangNano-9K-example\hdmi\src\hdmi.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>D:\FPGA\TangNano-9K-example\hdmi\src\hdmi.sdc</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NR-LV9QN88PC6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NR-9</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Fri Apr 19 15:27:09 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 1.14V 85C C6/I5</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.26V 0C C6/I5</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>3969</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>2606</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>57</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>81</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>3</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>clk_osc</td>
<td>Base</td>
<td>37.037</td>
<td>27.000
<td>0.000</td>
<td>18.518</td>
<td></td>
<td></td>
<td>clk </td>
</tr>
<tr>
<td>tck_pad_i</td>
<td>Base</td>
<td>50.000</td>
<td>20.000
<td>0.000</td>
<td>25.000</td>
<td></td>
<td></td>
<td>gw_gao_inst_0/tck_ibuf/I </td>
</tr>
<tr>
<td>controller/W_scan_seq_pls</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q </td>
</tr>
<tr>
<td>controller/n50_21</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>controller/n50_s1/F </td>
</tr>
<tr>
<td>sclk_5</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>sclk_s2/Q </td>
</tr>
<tr>
<td>controller/W_TXSET</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>controller/pls/W_TXSET_s/F </td>
</tr>
<tr>
<td>joystick_clk_d_4</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>controller/pls/joystick_clk_d_s0/F </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>7.936</td>
<td>126.000
<td>0.000</td>
<td>3.968</td>
<td>clk_ibuf/I</td>
<td>clk_osc</td>
<td>u_pll/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>7.936</td>
<td>126.000
<td>0.000</td>
<td>3.968</td>
<td>clk_ibuf/I</td>
<td>clk_osc</td>
<td>u_pll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>15.873</td>
<td>63.000
<td>0.000</td>
<td>7.936</td>
<td>clk_ibuf/I</td>
<td>clk_osc</td>
<td>u_pll/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>23.809</td>
<td>42.000
<td>0.000</td>
<td>11.905</td>
<td>clk_ibuf/I</td>
<td>clk_osc</td>
<td>u_pll/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>39.682</td>
<td>25.200
<td>0.000</td>
<td>19.841</td>
<td>u_pll/rpll_inst/CLKOUT</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk_osc</td>
<td>27.000(MHz)</td>
<td>107.449(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>tck_pad_i</td>
<td>20.000(MHz)</td>
<td>60.496(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>controller/n50_21</td>
<td>50.000(MHz)</td>
<td>143.295(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>sclk_5</td>
<td>50.000(MHz)</td>
<td>101.062(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>controller/W_TXSET</td>
<td>50.000(MHz)</td>
<td>126.117(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
<tr>
<td>6</td>
<td>joystick_clk_d_4</td>
<td>50.000(MHz)</td>
<td>305.315(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>7</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>25.200(MHz)</td>
<td>39.444(MHz)</td>
<td>17</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of controller/W_scan_seq_pls!</h4>
<h4>No timing paths to get frequency of u_pll/rpll_inst/CLKOUT.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_pll/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>clk_osc</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk_osc</td>
<td>Hold</td>
<td>-0.185</td>
<td>1</td>
</tr>
<tr>
<td>tck_pad_i</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>tck_pad_i</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/W_scan_seq_pls</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/W_scan_seq_pls</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/n50_21</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/n50_21</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sclk_5</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sclk_5</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/W_TXSET</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/W_TXSET</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>joystick_clk_d_4</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>joystick_clk_d_4</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-13.551</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>axis_xpos_0_s2/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>13.005</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-13.355</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>axis_ypos_0_s2/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>12.809</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-12.307</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout1_3_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>11.761</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>4</td>
<td>-12.261</td>
<td>controller/O_RXD_1_6_s1/Q</td>
<td>spiout1_4_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>11.715</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>5</td>
<td>-11.913</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout1_1_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>11.367</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>6</td>
<td>-11.185</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout1_5_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>10.639</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>7</td>
<td>-11.041</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout1_0_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>10.495</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>8</td>
<td>-10.977</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout2_3_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>10.431</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>9</td>
<td>-10.870</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout2_4_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>10.324</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>10</td>
<td>-10.870</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout1_6_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>10.324</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>11</td>
<td>-10.327</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout2_2_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>9.781</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>12</td>
<td>-10.327</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout1_2_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>9.781</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>13</td>
<td>-10.196</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>psstatus_0_s2/CE</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>10.006</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>14</td>
<td>-9.598</td>
<td>controller/O_RXD_1_6_s1/Q</td>
<td>psstatus_0_s2/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>9.052</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>15</td>
<td>-9.499</td>
<td>controller/O_RXD_2_0_s1/Q</td>
<td>direct_0_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>8.953</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>16</td>
<td>-8.834</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout2_5_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>8.288</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>17</td>
<td>-8.834</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>spiout2_6_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>8.288</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>18</td>
<td>-8.701</td>
<td>controller/O_RXD_1_0_s1/Q</td>
<td>axis_xpos_3_s2/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>8.155</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>19</td>
<td>-8.701</td>
<td>controller/O_RXD_1_0_s1/Q</td>
<td>axis_ypos_3_s2/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>8.155</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>20</td>
<td>-8.030</td>
<td>controller/O_RXD_2_0_s1/Q</td>
<td>spiout2_0_s0/D</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>7.484</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>21</td>
<td>-8.000</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE</td>
<td>tck_pad_i:[R]</td>
<td>clk_osc:[R]</td>
<td>1.850</td>
<td>2.099</td>
<td>7.677</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>22</td>
<td>-7.919</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE</td>
<td>tck_pad_i:[R]</td>
<td>clk_osc:[R]</td>
<td>1.850</td>
<td>2.099</td>
<td>7.596</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>23</td>
<td>-7.809</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/D</td>
<td>tck_pad_i:[R]</td>
<td>clk_osc:[R]</td>
<td>1.850</td>
<td>2.099</td>
<td>7.130</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>24</td>
<td>-7.786</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D</td>
<td>tck_pad_i:[R]</td>
<td>clk_osc:[R]</td>
<td>1.850</td>
<td>2.099</td>
<td>7.106</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>25</td>
<td>-7.737</td>
<td>controller/O_RXD_2_6_s1/Q</td>
<td>direct_0_s0/CE</td>
<td>controller/n50_21:[F]</td>
<td>clk_osc:[R]</td>
<td>0.369</td>
<td>0.485</td>
<td>7.548</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-0.683</td>
<td>controller/txd/n4_s5/I3</td>
<td>sclk_s2/D</td>
<td>sclk_5:[R]</td>
<td>clk_osc:[R]</td>
<td>-0.001</td>
<td>-1.029</td>
<td>0.374</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-0.375</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D</td>
<td>clk_osc:[R]</td>
<td>tck_pad_i:[R]</td>
<td>0.003</td>
<td>-1.626</td>
<td>1.282</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-0.185</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/D</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/D</td>
<td>clk_osc:[R]</td>
<td>clk_osc:[R]</td>
<td>0.000</td>
<td>-0.185</td>
<td>0.000</td>
</tr>
<tr>
<td>4</td>
<td>0.562</td>
<td>svo_hdmi_inst/svo_term/oresetn_s0/Q</td>
<td>svo_hdmi_inst/svo_term/p1_xpos_8_s0/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.577</td>
</tr>
<tr>
<td>5</td>
<td>0.575</td>
<td>svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s2/Q</td>
<td>svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s8/AD[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.590</td>
</tr>
<tr>
<td>6</td>
<td>0.599</td>
<td>status_0_s3/Q</td>
<td>wdata_0_s1/CE</td>
<td>clk_osc:[R]</td>
<td>clk_osc:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.614</td>
</tr>
<tr>
<td>7</td>
<td>0.599</td>
<td>status_0_s3/Q</td>
<td>wdata_1_s1/CE</td>
<td>clk_osc:[R]</td>
<td>clk_osc:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.614</td>
</tr>
<tr>
<td>8</td>
<td>0.599</td>
<td>status_0_s3/Q</td>
<td>wdata_4_s1/CE</td>
<td>clk_osc:[R]</td>
<td>clk_osc:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.614</td>
</tr>
<tr>
<td>9</td>
<td>0.670</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/D</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/D</td>
<td>sclk_5:[R]</td>
<td>clk_osc:[R]</td>
<td>-0.001</td>
<td>-1.029</td>
<td>1.728</td>
</tr>
<tr>
<td>10</td>
<td>0.693</td>
<td>controller/pls/O_byte_cnt_0_s0/RESET</td>
<td>controller/pls/O_byte_cnt_0_s0/RESET</td>
<td>controller/W_scan_seq_pls:[R]</td>
<td>sclk_5:[R]</td>
<td>0.000</td>
<td>-1.037</td>
<td>1.776</td>
</tr>
<tr>
<td>11</td>
<td>0.693</td>
<td>controller/pls/O_byte_cnt_1_s0/RESET</td>
<td>controller/pls/O_byte_cnt_1_s0/RESET</td>
<td>controller/W_scan_seq_pls:[R]</td>
<td>sclk_5:[R]</td>
<td>0.000</td>
<td>-1.037</td>
<td>1.776</td>
</tr>
<tr>
<td>12</td>
<td>0.693</td>
<td>controller/pls/O_byte_cnt_2_s0/RESET</td>
<td>controller/pls/O_byte_cnt_2_s0/RESET</td>
<td>controller/W_scan_seq_pls:[R]</td>
<td>sclk_5:[R]</td>
<td>0.000</td>
<td>-1.037</td>
<td>1.776</td>
</tr>
<tr>
<td>13</td>
<td>0.693</td>
<td>controller/pls/O_byte_cnt_3_s0/RESET</td>
<td>controller/pls/O_byte_cnt_3_s0/RESET</td>
<td>controller/W_scan_seq_pls:[R]</td>
<td>sclk_5:[R]</td>
<td>0.000</td>
<td>-1.037</td>
<td>1.776</td>
</tr>
<tr>
<td>14</td>
<td>0.693</td>
<td>controller/pls/psSEL_s0/RESET</td>
<td>controller/pls/psSEL_s0/RESET</td>
<td>controller/W_scan_seq_pls:[R]</td>
<td>sclk_5:[R]</td>
<td>0.000</td>
<td>-1.037</td>
<td>1.776</td>
</tr>
<tr>
<td>15</td>
<td>0.708</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D</td>
<td>clk_osc:[R]</td>
<td>clk_osc:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>16</td>
<td>0.708</td>
<td>uart_inst/tx_inst/send_bit_cnt_0_s3/Q</td>
<td>uart_inst/tx_inst/send_bit_cnt_0_s3/D</td>
<td>clk_osc:[R]</td>
<td>clk_osc:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>17</td>
<td>0.708</td>
<td>uart_inst/tx_inst/send_bit_cnt_3_s1/Q</td>
<td>uart_inst/tx_inst/send_bit_cnt_3_s1/D</td>
<td>clk_osc:[R]</td>
<td>clk_osc:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>18</td>
<td>0.708</td>
<td>axis_xpos_3_s2/Q</td>
<td>axis_xpos_3_s2/D</td>
<td>clk_osc:[R]</td>
<td>clk_osc:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>19</td>
<td>0.708</td>
<td>axis_xpos_0_s2/Q</td>
<td>axis_xpos_0_s2/D</td>
<td>clk_osc:[R]</td>
<td>clk_osc:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>20</td>
<td>0.708</td>
<td>svo_hdmi_inst/svo_enc/vcursor_13_s0/Q</td>
<td>svo_hdmi_inst/svo_enc/vcursor_13_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>21</td>
<td>0.708</td>
<td>svo_hdmi_inst/svo_enc/hcursor_13_s0/Q</td>
<td>svo_hdmi_inst/svo_enc/hcursor_13_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>22</td>
<td>0.708</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_1_s0/Q</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_1_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>23</td>
<td>0.708</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_7_s0/Q</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_7_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>24</td>
<td>0.708</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_11_s0/Q</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_11_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>25</td>
<td>0.708</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_13_s0/Q</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_13_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-0.431</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>tck_pad_i:[R]</td>
<td>0.001</td>
<td>-2.078</td>
<td>2.437</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-0.431</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>tck_pad_i:[R]</td>
<td>0.001</td>
<td>-2.078</td>
<td>2.437</td>
</tr>
<tr>
<td>3</td>
<td>0.398</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[0]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>3.968</td>
<td>-1.210</td>
<td>4.705</td>
</tr>
<tr>
<td>4</td>
<td>0.398</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[1]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>3.968</td>
<td>-1.210</td>
<td>4.705</td>
</tr>
<tr>
<td>5</td>
<td>0.398</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[2]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>3.968</td>
<td>-1.210</td>
<td>4.705</td>
</tr>
<tr>
<td>6</td>
<td>0.565</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>tck_pad_i:[R]</td>
<td>0.001</td>
<td>-2.078</td>
<td>1.440</td>
</tr>
<tr>
<td>7</td>
<td>4.360</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[0]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>7.936</td>
<td>-1.203</td>
<td>4.705</td>
</tr>
<tr>
<td>8</td>
<td>4.360</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[1]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>7.936</td>
<td>-1.203</td>
<td>4.705</td>
</tr>
<tr>
<td>9</td>
<td>4.360</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[2]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>7.936</td>
<td>-1.203</td>
<td>4.705</td>
</tr>
<tr>
<td>10</td>
<td>13.268</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>5.187</td>
</tr>
<tr>
<td>11</td>
<td>14.736</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>3.718</td>
</tr>
<tr>
<td>12</td>
<td>15.211</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>3.244</td>
</tr>
<tr>
<td>13</td>
<td>15.211</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>3.244</td>
</tr>
<tr>
<td>14</td>
<td>15.211</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>3.244</td>
</tr>
<tr>
<td>15</td>
<td>16.041</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>2.414</td>
</tr>
<tr>
<td>16</td>
<td>16.838</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>1.617</td>
</tr>
<tr>
<td>17</td>
<td>16.838</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>1.617</td>
</tr>
<tr>
<td>18</td>
<td>16.838</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>1.617</td>
</tr>
<tr>
<td>19</td>
<td>16.838</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>1.617</td>
</tr>
<tr>
<td>20</td>
<td>16.838</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>1.617</td>
</tr>
<tr>
<td>21</td>
<td>16.838</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>1.617</td>
</tr>
<tr>
<td>22</td>
<td>16.838</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>18.519</td>
<td>0.021</td>
<td>1.617</td>
</tr>
<tr>
<td>23</td>
<td>34.932</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[0]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.682</td>
<td>0.000</td>
<td>4.705</td>
</tr>
<tr>
<td>24</td>
<td>34.932</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[1]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.682</td>
<td>0.000</td>
<td>4.705</td>
</tr>
<tr>
<td>25</td>
<td>34.932</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[2]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.682</td>
<td>0.000</td>
<td>4.705</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>1.059</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>tck_pad_i:[R]</td>
<td>-1.850</td>
<td>-1.612</td>
<td>0.867</td>
</tr>
<tr>
<td>2</td>
<td>1.559</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[0]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.232</td>
<td>2.836</td>
</tr>
<tr>
<td>3</td>
<td>1.559</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[1]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.232</td>
<td>2.836</td>
</tr>
<tr>
<td>4</td>
<td>1.559</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[2]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.232</td>
<td>2.836</td>
</tr>
<tr>
<td>5</td>
<td>1.684</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>tck_pad_i:[R]</td>
<td>-1.850</td>
<td>-1.612</td>
<td>1.492</td>
</tr>
<tr>
<td>6</td>
<td>1.684</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>tck_pad_i:[R]</td>
<td>-1.850</td>
<td>-1.612</td>
<td>1.492</td>
</tr>
<tr>
<td>7</td>
<td>2.821</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[0]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.836</td>
</tr>
<tr>
<td>8</td>
<td>2.821</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[1]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.836</td>
</tr>
<tr>
<td>9</td>
<td>2.821</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[2]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.836</td>
</tr>
<tr>
<td>10</td>
<td>5.521</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[0]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>-3.968</td>
<td>-1.238</td>
<td>2.836</td>
</tr>
<tr>
<td>11</td>
<td>5.521</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[1]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>-3.968</td>
<td>-1.238</td>
<td>2.836</td>
</tr>
<tr>
<td>12</td>
<td>5.521</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
<td>svo_hdmi_inst/tmds_serdes[2]/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>-3.968</td>
<td>-1.238</td>
<td>2.836</td>
</tr>
<tr>
<td>13</td>
<td>19.119</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.603</td>
</tr>
<tr>
<td>14</td>
<td>19.119</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.603</td>
</tr>
<tr>
<td>15</td>
<td>19.123</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.607</td>
</tr>
<tr>
<td>16</td>
<td>19.123</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.607</td>
</tr>
<tr>
<td>17</td>
<td>19.123</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.607</td>
</tr>
<tr>
<td>18</td>
<td>19.123</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.607</td>
</tr>
<tr>
<td>19</td>
<td>19.123</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.607</td>
</tr>
<tr>
<td>20</td>
<td>19.367</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.851</td>
</tr>
<tr>
<td>21</td>
<td>19.367</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.851</td>
</tr>
<tr>
<td>22</td>
<td>19.367</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.851</td>
</tr>
<tr>
<td>23</td>
<td>19.367</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.851</td>
</tr>
<tr>
<td>24</td>
<td>19.367</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/triger_s0/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.851</td>
</tr>
<tr>
<td>25</td>
<td>19.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR</td>
<td>clk_osc:[F]</td>
<td>clk_osc:[R]</td>
<td>-18.518</td>
<td>0.013</td>
<td>0.874</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>7.399</td>
<td>8.649</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>controller/W_scan_seq_pls</td>
<td>controller/W_rxd_mask_s0</td>
</tr>
<tr>
<td>2</td>
<td>7.623</td>
<td>8.873</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>controller/W_TXSET</td>
<td>controller/cmd/pad_id_s0</td>
</tr>
<tr>
<td>3</td>
<td>7.623</td>
<td>8.873</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>controller/W_TXSET</td>
<td>controller/cmd/conf_done_s0</td>
</tr>
<tr>
<td>4</td>
<td>7.623</td>
<td>8.873</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>controller/W_TXSET</td>
<td>controller/cmd/O_TXD_DAT_7_s1</td>
</tr>
<tr>
<td>5</td>
<td>7.623</td>
<td>8.873</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>controller/W_TXSET</td>
<td>controller/cmd/O_TXD_DAT_6_s1</td>
</tr>
<tr>
<td>6</td>
<td>7.623</td>
<td>8.873</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>controller/W_TXSET</td>
<td>controller/cmd/O_TXD_DAT_4_s1</td>
</tr>
<tr>
<td>7</td>
<td>7.623</td>
<td>8.873</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>controller/W_TXSET</td>
<td>controller/cmd/O_TXD_DAT_1_s1</td>
</tr>
<tr>
<td>8</td>
<td>7.623</td>
<td>8.873</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>controller/W_TXSET</td>
<td>controller/cmd/conf_state_2_s1</td>
</tr>
<tr>
<td>9</td>
<td>7.623</td>
<td>8.873</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>controller/W_TXSET</td>
<td>controller/cmd/conf_state_0_s1</td>
</tr>
<tr>
<td>10</td>
<td>7.623</td>
<td>8.873</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>controller/W_TXSET</td>
<td>controller/cmd/conf_state_1_s1</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-13.551</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1384.715</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>axis_xpos_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.054</td>
<td>0.991</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[2][A]</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>1379.876</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C12[2][A]</td>
<td style=" background: #97FFFF;">n463_s17/F</td>
</tr>
<tr>
<td>1379.887</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[3][A]</td>
<td>n463_s12/I0</td>
</tr>
<tr>
<td>1380.709</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R8C12[3][A]</td>
<td style=" background: #97FFFF;">n463_s12/F</td>
</tr>
<tr>
<td>1381.213</td>
<td>0.504</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[3][B]</td>
<td>n431_s7/I2</td>
</tr>
<tr>
<td>1382.035</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C10[3][B]</td>
<td style=" background: #97FFFF;">n431_s7/F</td>
</tr>
<tr>
<td>1382.046</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[2][B]</td>
<td>n453_s13/I2</td>
</tr>
<tr>
<td>1383.078</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C10[2][B]</td>
<td style=" background: #97FFFF;">n453_s13/F</td>
</tr>
<tr>
<td>1383.893</td>
<td>0.816</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C7[1][A]</td>
<td>n453_s12/I2</td>
</tr>
<tr>
<td>1384.715</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C7[1][A]</td>
<td style=" background: #97FFFF;">n453_s12/F</td>
</tr>
<tr>
<td>1384.715</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C7[1][A]</td>
<td style=" font-weight:bold;">axis_xpos_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C7[1][A]</td>
<td>axis_xpos_0_s2/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>axis_xpos_0_s2</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C7[1][A]</td>
<td>axis_xpos_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 8.372, 64.376%; route: 4.175, 32.100%; tC2Q: 0.458, 3.524%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-13.355</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1384.519</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>axis_ypos_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.054</td>
<td>0.991</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[2][A]</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>1379.876</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C12[2][A]</td>
<td style=" background: #97FFFF;">n463_s17/F</td>
</tr>
<tr>
<td>1379.887</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[3][A]</td>
<td>n463_s12/I0</td>
</tr>
<tr>
<td>1380.709</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R8C12[3][A]</td>
<td style=" background: #97FFFF;">n463_s12/F</td>
</tr>
<tr>
<td>1381.213</td>
<td>0.504</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[3][B]</td>
<td>n431_s7/I2</td>
</tr>
<tr>
<td>1382.035</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C10[3][B]</td>
<td style=" background: #97FFFF;">n431_s7/F</td>
</tr>
<tr>
<td>1382.046</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[2][B]</td>
<td>n453_s13/I2</td>
</tr>
<tr>
<td>1383.078</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C10[2][B]</td>
<td style=" background: #97FFFF;">n453_s13/F</td>
</tr>
<tr>
<td>1383.893</td>
<td>0.816</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C7[0][B]</td>
<td>n462_s8/I1</td>
</tr>
<tr>
<td>1384.519</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C7[0][B]</td>
<td style=" background: #97FFFF;">n462_s8/F</td>
</tr>
<tr>
<td>1384.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C7[0][B]</td>
<td style=" font-weight:bold;">axis_ypos_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C7[0][B]</td>
<td>axis_ypos_0_s2/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>axis_ypos_0_s2</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C7[0][B]</td>
<td>axis_ypos_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 8.176, 63.831%; route: 4.175, 32.591%; tC2Q: 0.458, 3.578%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-12.307</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1383.471</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout1_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.054</td>
<td>0.991</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[2][A]</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>1379.876</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C12[2][A]</td>
<td style=" background: #97FFFF;">n463_s17/F</td>
</tr>
<tr>
<td>1379.887</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[2][B]</td>
<td>n437_s7/I2</td>
</tr>
<tr>
<td>1380.709</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C12[2][B]</td>
<td style=" background: #97FFFF;">n437_s7/F</td>
</tr>
<tr>
<td>1381.204</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[2][A]</td>
<td>n429_s8/I0</td>
</tr>
<tr>
<td>1382.231</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C10[2][A]</td>
<td style=" background: #97FFFF;">n429_s8/F</td>
</tr>
<tr>
<td>1382.650</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td>n429_s9/I2</td>
</tr>
<tr>
<td>1383.471</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" background: #97FFFF;">n429_s9/F</td>
</tr>
<tr>
<td>1383.471</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" font-weight:bold;">spiout1_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td>spiout1_3_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout1_3_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[0][B]</td>
<td>spiout1_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.544, 64.144%; route: 3.759, 31.959%; tC2Q: 0.458, 3.897%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-12.261</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1383.426</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_1_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout1_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C14[1][B]</td>
<td>controller/O_RXD_1_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R11C14[1][B]</td>
<td style=" font-weight:bold;">controller/O_RXD_1_6_s1/Q</td>
</tr>
<tr>
<td>1372.985</td>
<td>0.817</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C15[1][B]</td>
<td>n430_s10/I0</td>
</tr>
<tr>
<td>1374.047</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>R9C15[1][B]</td>
<td style=" background: #97FFFF;">n430_s10/F</td>
</tr>
<tr>
<td>1374.479</td>
<td>0.433</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C14[3][B]</td>
<td>n440_s7/I2</td>
</tr>
<tr>
<td>1375.578</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>3</td>
<td>R9C14[3][B]</td>
<td style=" background: #97FFFF;">n440_s7/F</td>
</tr>
<tr>
<td>1376.073</td>
<td>0.495</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>n432_s7/I2</td>
</tr>
<tr>
<td>1377.099</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R9C12[2][A]</td>
<td style=" background: #97FFFF;">n432_s7/F</td>
</tr>
<tr>
<td>1377.521</td>
<td>0.423</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td>n463_s14/I3</td>
</tr>
<tr>
<td>1378.547</td>
<td>1.026</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R9C11[0][A]</td>
<td style=" background: #97FFFF;">n463_s14/F</td>
</tr>
<tr>
<td>1378.972</td>
<td>0.425</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][B]</td>
<td>n429_s7/I0</td>
</tr>
<tr>
<td>1380.071</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R9C12[0][B]</td>
<td style=" background: #97FFFF;">n429_s7/F</td>
</tr>
<tr>
<td>1380.566</td>
<td>0.495</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[3][A]</td>
<td>n428_s9/I2</td>
</tr>
<tr>
<td>1381.665</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[3][A]</td>
<td style=" background: #97FFFF;">n428_s9/F</td>
</tr>
<tr>
<td>1382.800</td>
<td>1.135</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[0][A]</td>
<td>n428_s6/I3</td>
</tr>
<tr>
<td>1383.426</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C10[0][A]</td>
<td style=" background: #97FFFF;">n428_s6/F</td>
</tr>
<tr>
<td>1383.426</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[0][A]</td>
<td style=" font-weight:bold;">spiout1_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C10[0][A]</td>
<td>spiout1_4_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout1_4_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C10[0][A]</td>
<td>spiout1_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.036, 60.057%; route: 4.221, 36.031%; tC2Q: 0.458, 3.912%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-11.913</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1383.078</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout1_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.054</td>
<td>0.991</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[2][A]</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>1379.876</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C12[2][A]</td>
<td style=" background: #97FFFF;">n463_s17/F</td>
</tr>
<tr>
<td>1379.887</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[3][A]</td>
<td>n463_s12/I0</td>
</tr>
<tr>
<td>1380.709</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R8C12[3][A]</td>
<td style=" background: #97FFFF;">n463_s12/F</td>
</tr>
<tr>
<td>1381.213</td>
<td>0.504</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[3][B]</td>
<td>n431_s7/I2</td>
</tr>
<tr>
<td>1382.035</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C10[3][B]</td>
<td style=" background: #97FFFF;">n431_s7/F</td>
</tr>
<tr>
<td>1382.046</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[1][B]</td>
<td>n431_s9/I2</td>
</tr>
<tr>
<td>1383.078</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C10[1][B]</td>
<td style=" background: #97FFFF;">n431_s9/F</td>
</tr>
<tr>
<td>1383.078</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[1][B]</td>
<td style=" font-weight:bold;">spiout1_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C10[1][B]</td>
<td>spiout1_1_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout1_1_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C10[1][B]</td>
<td>spiout1_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.550, 66.419%; route: 3.359, 29.549%; tC2Q: 0.458, 4.032%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-11.185</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1382.350</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout1_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.219</td>
<td>1.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>psstatus_2_s5/I0</td>
</tr>
<tr>
<td>1380.251</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C12[0][A]</td>
<td style=" background: #97FFFF;">psstatus_2_s5/F</td>
</tr>
<tr>
<td>1380.746</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td>psstatus_2_s4/I0</td>
</tr>
<tr>
<td>1381.372</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C10[2][A]</td>
<td style=" background: #97FFFF;">psstatus_2_s4/F</td>
</tr>
<tr>
<td>1382.350</td>
<td>0.978</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td style=" font-weight:bold;">spiout1_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td>spiout1_5_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout1_5_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[2][B]</td>
<td>spiout1_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.710, 53.669%; route: 4.471, 42.023%; tC2Q: 0.458, 4.308%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-11.041</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1382.205</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout1_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.219</td>
<td>1.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>psstatus_2_s5/I0</td>
</tr>
<tr>
<td>1380.251</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C12[0][A]</td>
<td style=" background: #97FFFF;">psstatus_2_s5/F</td>
</tr>
<tr>
<td>1380.746</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td>psstatus_2_s4/I0</td>
</tr>
<tr>
<td>1381.372</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C10[2][A]</td>
<td style=" background: #97FFFF;">psstatus_2_s4/F</td>
</tr>
<tr>
<td>1381.383</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td>n432_s8/I2</td>
</tr>
<tr>
<td>1382.205</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td style=" background: #97FFFF;">n432_s8/F</td>
</tr>
<tr>
<td>1382.205</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td style=" font-weight:bold;">spiout1_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td>spiout1_0_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout1_0_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[0][A]</td>
<td>spiout1_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.532, 62.241%; route: 3.504, 33.391%; tC2Q: 0.458, 4.367%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-10.977</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1382.142</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout2_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.054</td>
<td>0.991</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[2][A]</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>1379.876</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C12[2][A]</td>
<td style=" background: #97FFFF;">n463_s17/F</td>
</tr>
<tr>
<td>1379.887</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[2][B]</td>
<td>n437_s7/I2</td>
</tr>
<tr>
<td>1380.689</td>
<td>0.802</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R8C12[2][B]</td>
<td style=" background: #97FFFF;">n437_s7/F</td>
</tr>
<tr>
<td>1381.110</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C13[2][A]</td>
<td>n437_s6/I1</td>
</tr>
<tr>
<td>1382.142</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R8C13[2][A]</td>
<td style=" background: #97FFFF;">n437_s6/F</td>
</tr>
<tr>
<td>1382.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C13[2][A]</td>
<td style=" font-weight:bold;">spiout2_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C13[2][A]</td>
<td>spiout2_3_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout2_3_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C13[2][A]</td>
<td>spiout2_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.708, 64.306%; route: 3.265, 31.300%; tC2Q: 0.458, 4.394%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-10.870</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1382.035</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout2_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.054</td>
<td>0.991</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[2][A]</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>1379.876</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C12[2][A]</td>
<td style=" background: #97FFFF;">n463_s17/F</td>
</tr>
<tr>
<td>1379.887</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[3][A]</td>
<td>n463_s12/I0</td>
</tr>
<tr>
<td>1380.709</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R8C12[3][A]</td>
<td style=" background: #97FFFF;">n463_s12/F</td>
</tr>
<tr>
<td>1381.213</td>
<td>0.504</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[1][A]</td>
<td>n436_s9/I0</td>
</tr>
<tr>
<td>1382.035</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C10[1][A]</td>
<td style=" background: #97FFFF;">n436_s9/F</td>
</tr>
<tr>
<td>1382.035</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[1][A]</td>
<td style=" font-weight:bold;">spiout2_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C10[1][A]</td>
<td>spiout2_4_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout2_4_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C10[1][A]</td>
<td>spiout2_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.518, 63.133%; route: 3.348, 32.428%; tC2Q: 0.458, 4.439%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-10.870</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1382.035</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout1_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.054</td>
<td>0.991</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[2][A]</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>1379.876</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C12[2][A]</td>
<td style=" background: #97FFFF;">n463_s17/F</td>
</tr>
<tr>
<td>1379.887</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[3][A]</td>
<td>n463_s12/I0</td>
</tr>
<tr>
<td>1380.709</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R8C12[3][A]</td>
<td style=" background: #97FFFF;">n463_s12/F</td>
</tr>
<tr>
<td>1381.213</td>
<td>0.504</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[0][B]</td>
<td>n463_s18/I2</td>
</tr>
<tr>
<td>1382.035</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C10[0][B]</td>
<td style=" background: #97FFFF;">n463_s18/F</td>
</tr>
<tr>
<td>1382.035</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[0][B]</td>
<td style=" font-weight:bold;">spiout1_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C10[0][B]</td>
<td>spiout1_6_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout1_6_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C10[0][B]</td>
<td>spiout1_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.518, 63.133%; route: 3.348, 32.428%; tC2Q: 0.458, 4.439%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-10.327</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1381.491</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout2_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.219</td>
<td>1.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>psstatus_2_s5/I0</td>
</tr>
<tr>
<td>1380.245</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R9C12[0][A]</td>
<td style=" background: #97FFFF;">psstatus_2_s5/F</td>
</tr>
<tr>
<td>1380.669</td>
<td>0.425</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td>n438_s11/I3</td>
</tr>
<tr>
<td>1381.491</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td style=" background: #97FFFF;">n438_s11/F</td>
</tr>
<tr>
<td>1381.491</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td style=" font-weight:bold;">spiout2_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td>spiout2_2_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout2_2_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C11[0][B]</td>
<td>spiout2_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.900, 60.322%; route: 3.423, 34.993%; tC2Q: 0.458, 4.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-10.327</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1381.491</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout1_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.219</td>
<td>1.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>psstatus_2_s5/I0</td>
</tr>
<tr>
<td>1380.245</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R9C12[0][A]</td>
<td style=" background: #97FFFF;">psstatus_2_s5/F</td>
</tr>
<tr>
<td>1380.669</td>
<td>0.425</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td>n430_s12/I2</td>
</tr>
<tr>
<td>1381.491</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td style=" background: #97FFFF;">n430_s12/F</td>
</tr>
<tr>
<td>1381.491</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td style=" font-weight:bold;">spiout1_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td>spiout1_2_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout1_2_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C11[1][A]</td>
<td>spiout1_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.900, 60.322%; route: 3.423, 34.993%; tC2Q: 0.458, 4.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-10.196</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1381.717</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.521</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>psstatus_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.219</td>
<td>1.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>psstatus_2_s5/I0</td>
</tr>
<tr>
<td>1380.251</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C12[0][A]</td>
<td style=" background: #97FFFF;">psstatus_2_s5/F</td>
</tr>
<tr>
<td>1380.746</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td>psstatus_2_s4/I0</td>
</tr>
<tr>
<td>1381.371</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R9C10[2][A]</td>
<td style=" background: #97FFFF;">psstatus_2_s4/F</td>
</tr>
<tr>
<td>1381.717</td>
<td>0.346</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" font-weight:bold;">psstatus_0_s2/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td>psstatus_0_s2/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>psstatus_0_s2</td>
</tr>
<tr>
<td>1371.521</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[1][A]</td>
<td>psstatus_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.709, 57.054%; route: 3.839, 38.365%; tC2Q: 0.458, 4.580%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-9.598</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1380.762</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_1_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>psstatus_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C14[1][B]</td>
<td>controller/O_RXD_1_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R11C14[1][B]</td>
<td style=" font-weight:bold;">controller/O_RXD_1_6_s1/Q</td>
</tr>
<tr>
<td>1372.985</td>
<td>0.817</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C15[1][B]</td>
<td>n430_s10/I0</td>
</tr>
<tr>
<td>1374.047</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>R9C15[1][B]</td>
<td style=" background: #97FFFF;">n430_s10/F</td>
</tr>
<tr>
<td>1374.479</td>
<td>0.433</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C14[3][B]</td>
<td>n440_s7/I2</td>
</tr>
<tr>
<td>1375.578</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>3</td>
<td>R9C14[3][B]</td>
<td style=" background: #97FFFF;">n440_s7/F</td>
</tr>
<tr>
<td>1376.073</td>
<td>0.495</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>n432_s7/I2</td>
</tr>
<tr>
<td>1377.099</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R9C12[2][A]</td>
<td style=" background: #97FFFF;">n432_s7/F</td>
</tr>
<tr>
<td>1377.521</td>
<td>0.423</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td>n463_s14/I3</td>
</tr>
<tr>
<td>1378.547</td>
<td>1.026</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R9C11[0][A]</td>
<td style=" background: #97FFFF;">n463_s14/F</td>
</tr>
<tr>
<td>1378.972</td>
<td>0.425</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td>n465_s9/I0</td>
</tr>
<tr>
<td>1379.794</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R9C10[1][B]</td>
<td style=" background: #97FFFF;">n465_s9/F</td>
</tr>
<tr>
<td>1380.762</td>
<td>0.968</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" font-weight:bold;">psstatus_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td>psstatus_0_s2/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>psstatus_0_s2</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[1][A]</td>
<td>psstatus_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.034, 55.615%; route: 3.559, 39.321%; tC2Q: 0.458, 5.064%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-9.499</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1380.664</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>direct_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>controller/O_RXD_2_0_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>3</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_0_s1/Q</td>
</tr>
<tr>
<td>1373.631</td>
<td>1.462</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C14[2][A]</td>
<td>n412_s2/I0</td>
</tr>
<tr>
<td>1374.663</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C14[2][A]</td>
<td style=" background: #97FFFF;">n412_s2/F</td>
</tr>
<tr>
<td>1375.162</td>
<td>0.499</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][A]</td>
<td>n412_s1/I2</td>
</tr>
<tr>
<td>1375.984</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[0][A]</td>
<td style=" background: #97FFFF;">n412_s1/F</td>
</tr>
<tr>
<td>1377.464</td>
<td>1.479</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[2][A]</td>
<td>n416_s0/I1</td>
</tr>
<tr>
<td>1378.562</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C11[2][A]</td>
<td style=" background: #97FFFF;">n416_s0/F</td>
</tr>
<tr>
<td>1380.664</td>
<td>2.101</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C17[0][B]</td>
<td style=" font-weight:bold;">direct_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C17[0][B]</td>
<td>direct_0_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>direct_0_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C17[0][B]</td>
<td>direct_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.953, 32.982%; route: 5.542, 61.899%; tC2Q: 0.458, 5.119%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-8.834</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1379.999</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout2_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.373</td>
<td>1.310</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>n435_s7/I2</td>
</tr>
<tr>
<td>1379.999</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td style=" background: #97FFFF;">n435_s7/F</td>
</tr>
<tr>
<td>1379.999</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td style=" font-weight:bold;">spiout2_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>spiout2_5_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout2_5_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>spiout2_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 56.440%; route: 3.152, 38.030%; tC2Q: 0.458, 5.530%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-8.834</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1379.999</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout2_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1379.373</td>
<td>1.310</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td>n434_s8/I2</td>
</tr>
<tr>
<td>1379.999</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td style=" background: #97FFFF;">n434_s8/F</td>
</tr>
<tr>
<td>1379.999</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td style=" font-weight:bold;">spiout2_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td>spiout2_6_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout2_6_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C13[1][B]</td>
<td>spiout2_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 56.440%; route: 3.152, 38.030%; tC2Q: 0.458, 5.530%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-8.701</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1379.866</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_1_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>axis_xpos_3_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>controller/O_RXD_1_0_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>R9C12[1][B]</td>
<td style=" font-weight:bold;">controller/O_RXD_1_0_s1/Q</td>
</tr>
<tr>
<td>1372.980</td>
<td>0.812</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C15[0][B]</td>
<td>n438_s9/I0</td>
</tr>
<tr>
<td>1374.079</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C15[0][B]</td>
<td style=" background: #97FFFF;">n438_s9/F</td>
</tr>
<tr>
<td>1374.090</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C15[1][A]</td>
<td>n439_s8/I2</td>
</tr>
<tr>
<td>1375.189</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C15[1][A]</td>
<td style=" background: #97FFFF;">n439_s8/F</td>
</tr>
<tr>
<td>1375.206</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C15[0][A]</td>
<td>n451_s12/I2</td>
</tr>
<tr>
<td>1375.832</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R9C15[0][A]</td>
<td style=" background: #97FFFF;">n451_s12/F</td>
</tr>
<tr>
<td>1376.987</td>
<td>1.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[2][B]</td>
<td>n453_s14/I0</td>
</tr>
<tr>
<td>1378.019</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R8C11[2][B]</td>
<td style=" background: #97FFFF;">n453_s14/F</td>
</tr>
<tr>
<td>1378.834</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C8[1][A]</td>
<td>n450_s9/I0</td>
</tr>
<tr>
<td>1379.866</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C8[1][A]</td>
<td style=" background: #97FFFF;">n450_s9/F</td>
</tr>
<tr>
<td>1379.866</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C8[1][A]</td>
<td style=" font-weight:bold;">axis_xpos_3_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C8[1][A]</td>
<td>axis_xpos_3_s2/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>axis_xpos_3_s2</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C8[1][A]</td>
<td>axis_xpos_3_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.888, 59.936%; route: 2.809, 34.444%; tC2Q: 0.458, 5.620%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-8.701</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1379.866</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_1_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>axis_ypos_3_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>controller/O_RXD_1_0_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>R9C12[1][B]</td>
<td style=" font-weight:bold;">controller/O_RXD_1_0_s1/Q</td>
</tr>
<tr>
<td>1372.980</td>
<td>0.812</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C15[0][B]</td>
<td>n438_s9/I0</td>
</tr>
<tr>
<td>1374.079</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C15[0][B]</td>
<td style=" background: #97FFFF;">n438_s9/F</td>
</tr>
<tr>
<td>1374.090</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C15[1][A]</td>
<td>n439_s8/I2</td>
</tr>
<tr>
<td>1375.189</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C15[1][A]</td>
<td style=" background: #97FFFF;">n439_s8/F</td>
</tr>
<tr>
<td>1375.206</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C15[0][A]</td>
<td>n451_s12/I2</td>
</tr>
<tr>
<td>1375.832</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R9C15[0][A]</td>
<td style=" background: #97FFFF;">n451_s12/F</td>
</tr>
<tr>
<td>1376.987</td>
<td>1.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[2][B]</td>
<td>n453_s14/I0</td>
</tr>
<tr>
<td>1378.019</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R8C11[2][B]</td>
<td style=" background: #97FFFF;">n453_s14/F</td>
</tr>
<tr>
<td>1378.834</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C8[1][B]</td>
<td>n459_s13/I0</td>
</tr>
<tr>
<td>1379.866</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C8[1][B]</td>
<td style=" background: #97FFFF;">n459_s13/F</td>
</tr>
<tr>
<td>1379.866</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C8[1][B]</td>
<td style=" font-weight:bold;">axis_ypos_3_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C8[1][B]</td>
<td>axis_ypos_3_s2/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>axis_ypos_3_s2</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C8[1][B]</td>
<td>axis_ypos_3_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.888, 59.936%; route: 2.809, 34.444%; tC2Q: 0.458, 5.620%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-8.030</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1379.194</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.164</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout2_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>controller/O_RXD_2_0_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>3</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_0_s1/Q</td>
</tr>
<tr>
<td>1373.631</td>
<td>1.462</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C14[2][A]</td>
<td>n412_s2/I0</td>
</tr>
<tr>
<td>1374.663</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C14[2][A]</td>
<td style=" background: #97FFFF;">n412_s2/F</td>
</tr>
<tr>
<td>1375.162</td>
<td>0.499</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][A]</td>
<td>n412_s1/I2</td>
</tr>
<tr>
<td>1375.984</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[0][A]</td>
<td style=" background: #97FFFF;">n412_s1/F</td>
</tr>
<tr>
<td>1377.464</td>
<td>1.479</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>n440_s8/I1</td>
</tr>
<tr>
<td>1378.562</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td style=" background: #97FFFF;">n440_s8/F</td>
</tr>
<tr>
<td>1378.568</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[1][A]</td>
<td>n440_s11/I3</td>
</tr>
<tr>
<td>1379.194</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C11[1][A]</td>
<td style=" background: #97FFFF;">n440_s11/F</td>
</tr>
<tr>
<td>1379.194</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[1][A]</td>
<td style=" font-weight:bold;">spiout2_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[1][A]</td>
<td>spiout2_0_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spiout2_0_s0</td>
</tr>
<tr>
<td>1371.165</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C11[1][A]</td>
<td>spiout2_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.579, 47.825%; route: 3.446, 46.050%; tC2Q: 0.458, 6.125%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-8.000</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1861.002</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1853.002</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/trigger_seq_start_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1850.000</td>
<td>1850.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1850.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>1850.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>1850.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>1850.982</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1851.964</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>1853.325</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C15[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK</td>
</tr>
<tr>
<td>1853.783</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R17C15[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q</td>
</tr>
<tr>
<td>1855.245</td>
<td>1.462</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R20C16[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/n1113_s0/I1</td>
</tr>
<tr>
<td>1856.290</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C16[1][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/n1113_s0/COUT</td>
</tr>
<tr>
<td>1856.290</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R20C16[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/n1114_s0/CIN</td>
</tr>
<tr>
<td>1856.347</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C16[2][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/n1114_s0/COUT</td>
</tr>
<tr>
<td>1857.417</td>
<td>1.069</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C18[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/n1155_s1/I0</td>
</tr>
<tr>
<td>1858.449</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C18[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/n1155_s1/F</td>
</tr>
<tr>
<td>1858.454</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C18[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3</td>
</tr>
<tr>
<td>1859.480</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R20C18[3][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F</td>
</tr>
<tr>
<td>1861.002</td>
<td>1.522</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C18[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1851.850</td>
<td>1851.850</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1851.850</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1851.850</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1852.832</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1853.076</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C18[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK</td>
</tr>
<tr>
<td>1853.046</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/trigger_seq_start_s1</td>
</tr>
<tr>
<td>1853.002</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C18[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/trigger_seq_start_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.099</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.850</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.964, 59.066%; route: 1.361, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.160, 41.160%; route: 4.059, 52.870%; tC2Q: 0.458, 5.970%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.919</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1860.921</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1853.002</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1850.000</td>
<td>1850.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1850.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>1850.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>1850.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>1850.982</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1851.964</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>1853.325</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C14[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0/CLK</td>
</tr>
<tr>
<td>1853.783</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R14C14[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0/Q</td>
</tr>
<tr>
<td>1854.122</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C14[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s15/I1</td>
</tr>
<tr>
<td>1855.183</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R14C14[3][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s15/F</td>
</tr>
<tr>
<td>1855.602</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s9/I3</td>
</tr>
<tr>
<td>1856.424</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R14C15[0][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s9/F</td>
</tr>
<tr>
<td>1857.228</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s5/I2</td>
</tr>
<tr>
<td>1858.327</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>R15C16[1][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s5/F</td>
</tr>
<tr>
<td>1859.191</td>
<td>0.864</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0</td>
</tr>
<tr>
<td>1860.217</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R15C18[1][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F</td>
</tr>
<tr>
<td>1860.921</td>
<td>0.704</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C18[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1851.850</td>
<td>1851.850</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1851.850</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1851.850</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1852.832</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1853.076</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C18[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK</td>
</tr>
<tr>
<td>1853.046</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
<tr>
<td>1853.002</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C18[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.099</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.850</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.964, 59.066%; route: 1.361, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.008, 52.763%; route: 3.130, 41.204%; tC2Q: 0.458, 6.034%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.809</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1860.455</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1852.645</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1850.000</td>
<td>1850.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1850.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>1850.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>1850.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>1850.982</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1851.964</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>1853.325</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C14[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0/CLK</td>
</tr>
<tr>
<td>1853.783</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R14C14[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0/Q</td>
</tr>
<tr>
<td>1854.122</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C14[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s15/I1</td>
</tr>
<tr>
<td>1855.183</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R14C14[3][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s15/F</td>
</tr>
<tr>
<td>1855.602</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s9/I3</td>
</tr>
<tr>
<td>1856.424</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R14C15[0][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s9/F</td>
</tr>
<tr>
<td>1857.228</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s5/I2</td>
</tr>
<tr>
<td>1858.327</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>R15C16[1][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s5/F</td>
</tr>
<tr>
<td>1859.633</td>
<td>1.305</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C19[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s2/I3</td>
</tr>
<tr>
<td>1860.455</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R14C19[2][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s2/F</td>
</tr>
<tr>
<td>1860.455</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C19[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1851.850</td>
<td>1851.850</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1851.850</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1851.850</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1852.832</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1853.076</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C19[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLK</td>
</tr>
<tr>
<td>1853.046</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1</td>
</tr>
<tr>
<td>1852.646</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R14C19[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.099</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.850</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.964, 59.066%; route: 1.361, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.804, 53.352%; route: 2.868, 40.219%; tC2Q: 0.458, 6.428%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.786</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1860.431</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1852.645</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1850.000</td>
<td>1850.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1850.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>1850.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>1850.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>1850.982</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1851.964</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>1853.325</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C14[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0/CLK</td>
</tr>
<tr>
<td>1853.783</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R14C14[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_mem_addr_max_12_s0/Q</td>
</tr>
<tr>
<td>1854.122</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C14[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s15/I1</td>
</tr>
<tr>
<td>1855.183</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R14C14[3][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s15/F</td>
</tr>
<tr>
<td>1855.602</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s9/I3</td>
</tr>
<tr>
<td>1856.424</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R14C15[0][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s9/F</td>
</tr>
<tr>
<td>1857.228</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s5/I2</td>
</tr>
<tr>
<td>1858.327</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>R15C16[1][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n184_s5/F</td>
</tr>
<tr>
<td>1859.332</td>
<td>1.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C19[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n186_s1/I3</td>
</tr>
<tr>
<td>1860.431</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R15C19[1][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n186_s1/F</td>
</tr>
<tr>
<td>1860.431</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C19[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1851.850</td>
<td>1851.850</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1851.850</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1851.850</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1852.832</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1853.076</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C19[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK</td>
</tr>
<tr>
<td>1853.046</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1</td>
</tr>
<tr>
<td>1852.646</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C19[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.099</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.850</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.964, 59.066%; route: 1.361, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.081, 57.428%; route: 2.567, 36.122%; tC2Q: 0.458, 6.450%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.737</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1379.258</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1371.521</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>direct_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.000</td>
<td>1370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>1370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>R12C18[0][A]</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>1371.710</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>controller/O_RXD_2_6_s1/CLK</td>
</tr>
<tr>
<td>1372.169</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>6</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">controller/O_RXD_2_6_s1/Q</td>
</tr>
<tr>
<td>1373.973</td>
<td>1.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[0][B]</td>
<td>n416_s2/I0</td>
</tr>
<tr>
<td>1375.072</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[0][B]</td>
<td style=" background: #97FFFF;">n416_s2/F</td>
</tr>
<tr>
<td>1375.083</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][A]</td>
<td>n430_s11/I3</td>
</tr>
<tr>
<td>1376.182</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C16[2][A]</td>
<td style=" background: #97FFFF;">n430_s11/F</td>
</tr>
<tr>
<td>1376.198</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>1377.020</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">n436_s7/F</td>
</tr>
<tr>
<td>1377.031</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][A]</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>1378.063</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R8C16[3][A]</td>
<td style=" background: #97FFFF;">direct_1_s5/F</td>
</tr>
<tr>
<td>1378.085</td>
<td>0.022</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[3][B]</td>
<td>direct_1_s2/I0</td>
</tr>
<tr>
<td>1378.887</td>
<td>0.802</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R8C16[3][B]</td>
<td style=" background: #97FFFF;">direct_1_s2/F</td>
</tr>
<tr>
<td>1379.258</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C17[0][B]</td>
<td style=" font-weight:bold;">direct_0_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1370.369</td>
<td>1370.369</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1370.369</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1371.351</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1371.595</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C17[0][B]</td>
<td>direct_0_s0/CLK</td>
</tr>
<tr>
<td>1371.565</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>direct_0_s0</td>
</tr>
<tr>
<td>1371.521</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C17[0][B]</td>
<td>direct_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.485</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.369</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.854, 64.309%; route: 2.236, 29.619%; tC2Q: 0.458, 6.072%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.683</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1000.374</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1001.058</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/txd/n4_s5</td>
</tr>
<tr>
<td class="label">To</td>
<td>sclk_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sclk_5:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sclk_5</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>35</td>
<td>R9C18[1][A]</td>
<td>sclk_s2/Q</td>
</tr>
<tr>
<td>1000.002</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C18[1][A]</td>
<td style=" font-weight:bold;">controller/txd/n4_s5/I3</td>
</tr>
<tr>
<td>1000.374</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C18[1][A]</td>
<td style=" background: #97FFFF;">controller/txd/n4_s5/F</td>
</tr>
<tr>
<td>1000.374</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C18[1][A]</td>
<td style=" font-weight:bold;">sclk_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>999.999</td>
<td>999.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>999.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>999.999</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1000.843</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1001.028</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C18[1][A]</td>
<td>sclk_s2/CLK</td>
</tr>
<tr>
<td>1001.058</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sclk_s2</td>
</tr>
<tr>
<td>1001.058</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C18[1][A]</td>
<td>sclk_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 99.369%; route: 0.000, 0.000%; tC2Q: 0.002, 0.631%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.375</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3002.307</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3002.682</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2999.997</td>
<td>2999.997</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2999.997</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>2999.997</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>3000.841</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>3001.026</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C16[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK</td>
</tr>
<tr>
<td>3001.359</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R16C16[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q</td>
</tr>
<tr>
<td>3001.935</td>
<td>0.576</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C15[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/n1147_s1/I2</td>
</tr>
<tr>
<td>3002.307</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C15[2][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/n1147_s1/F</td>
</tr>
<tr>
<td>3002.307</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>3000.000</td>
<td>3000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>3000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>3000.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>3000.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>3000.844</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>3001.689</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>3002.655</td>
<td>0.966</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C15[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK</td>
</tr>
<tr>
<td>3002.685</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
<tr>
<td>3002.685</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C15[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.626</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.003</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 29.026%; route: 0.576, 44.966%; tC2Q: 0.333, 26.009%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.689, 63.613%; route: 0.966, 36.387%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.185</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.844</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOR17[A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.185</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 100.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.562</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.090</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/svo_term/oresetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/svo_term/p1_xpos_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[2][B]</td>
<td>svo_hdmi_inst/svo_term/oresetn_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>34</td>
<td>R18C22[2][B]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_term/oresetn_s0/Q</td>
</tr>
<tr>
<td>1.090</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_term/p1_xpos_8_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[0][A]</td>
<td>svo_hdmi_inst/svo_term/p1_xpos_8_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C22[0][A]</td>
<td>svo_hdmi_inst/svo_term/p1_xpos_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 42.211%; tC2Q: 0.333, 57.789%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.575</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.104</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s8</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C37[0][A]</td>
<td>svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s2/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R16C37[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s2/Q</td>
</tr>
<tr>
<td>1.104</td>
<td>0.257</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C37</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s8/AD[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C37</td>
<td>svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s8/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C37</td>
<td>svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s8</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.257, 43.543%; tC2Q: 0.333, 56.457%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.599</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.643</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>status_0_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>wdata_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C8[0][B]</td>
<td>status_0_s3/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>17</td>
<td>R8C8[0][B]</td>
<td style=" font-weight:bold;">status_0_s3/Q</td>
</tr>
<tr>
<td>1.643</td>
<td>0.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C9[0][B]</td>
<td style=" font-weight:bold;">wdata_0_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C9[0][B]</td>
<td>wdata_0_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C9[0][B]</td>
<td>wdata_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.281, 45.732%; tC2Q: 0.333, 54.268%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.599</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.643</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>status_0_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>wdata_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C8[0][B]</td>
<td>status_0_s3/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>17</td>
<td>R8C8[0][B]</td>
<td style=" font-weight:bold;">status_0_s3/Q</td>
</tr>
<tr>
<td>1.643</td>
<td>0.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C9[1][A]</td>
<td style=" font-weight:bold;">wdata_1_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C9[1][A]</td>
<td>wdata_1_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C9[1][A]</td>
<td>wdata_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.281, 45.732%; tC2Q: 0.333, 54.268%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.599</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.643</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>status_0_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>wdata_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C8[0][B]</td>
<td>status_0_s3/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>17</td>
<td>R8C8[0][B]</td>
<td style=" font-weight:bold;">status_0_s3/Q</td>
</tr>
<tr>
<td>1.643</td>
<td>0.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C9[0][A]</td>
<td style=" font-weight:bold;">wdata_4_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C9[0][A]</td>
<td>wdata_4_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C9[0][A]</td>
<td>wdata_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.281, 45.732%; tC2Q: 0.333, 54.268%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.670</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1001.728</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1001.058</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sclk_5:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sclk_5</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>35</td>
<td>R9C18[1][A]</td>
<td>sclk_s2/Q</td>
</tr>
<tr>
<td>1001.728</td>
<td>1.728</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C14[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>999.999</td>
<td>999.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>999.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>999.999</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1000.843</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1001.028</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C14[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK</td>
</tr>
<tr>
<td>1001.058</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0</td>
</tr>
<tr>
<td>1001.058</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C14[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.728, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.693</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.776</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.082</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/pls/O_byte_cnt_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>controller/pls/O_byte_cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/W_scan_seq_pls:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sclk_5:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>R11C18[0][A]</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>1.776</td>
<td>1.776</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[0][B]</td>
<td style=" font-weight:bold;">controller/pls/O_byte_cnt_0_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sclk_5</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>35</td>
<td>R9C18[1][A]</td>
<td>sclk_s2/Q</td>
</tr>
<tr>
<td>1.037</td>
<td>1.037</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[0][B]</td>
<td>controller/pls/O_byte_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>1.067</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>controller/pls/O_byte_cnt_0_s0</td>
</tr>
<tr>
<td>1.082</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C17[0][B]</td>
<td>controller/pls/O_byte_cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.037</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.776, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.037, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.693</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.776</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.082</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/pls/O_byte_cnt_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>controller/pls/O_byte_cnt_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/W_scan_seq_pls:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sclk_5:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>R11C18[0][A]</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>1.776</td>
<td>1.776</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[0][A]</td>
<td style=" font-weight:bold;">controller/pls/O_byte_cnt_1_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sclk_5</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>35</td>
<td>R9C18[1][A]</td>
<td>sclk_s2/Q</td>
</tr>
<tr>
<td>1.037</td>
<td>1.037</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[0][A]</td>
<td>controller/pls/O_byte_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>1.067</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>controller/pls/O_byte_cnt_1_s0</td>
</tr>
<tr>
<td>1.082</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C17[0][A]</td>
<td>controller/pls/O_byte_cnt_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.037</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.776, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.037, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.693</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.776</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.082</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/pls/O_byte_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>controller/pls/O_byte_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/W_scan_seq_pls:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sclk_5:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>R11C18[0][A]</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>1.776</td>
<td>1.776</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C15[2][A]</td>
<td style=" font-weight:bold;">controller/pls/O_byte_cnt_2_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sclk_5</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>35</td>
<td>R9C18[1][A]</td>
<td>sclk_s2/Q</td>
</tr>
<tr>
<td>1.037</td>
<td>1.037</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C15[2][A]</td>
<td>controller/pls/O_byte_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.067</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>controller/pls/O_byte_cnt_2_s0</td>
</tr>
<tr>
<td>1.082</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C15[2][A]</td>
<td>controller/pls/O_byte_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.037</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.776, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.037, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.693</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.776</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.082</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/pls/O_byte_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>controller/pls/O_byte_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/W_scan_seq_pls:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sclk_5:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>R11C18[0][A]</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>1.776</td>
<td>1.776</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C16[0][B]</td>
<td style=" font-weight:bold;">controller/pls/O_byte_cnt_3_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sclk_5</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>35</td>
<td>R9C18[1][A]</td>
<td>sclk_s2/Q</td>
</tr>
<tr>
<td>1.037</td>
<td>1.037</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C16[0][B]</td>
<td>controller/pls/O_byte_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>1.067</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>controller/pls/O_byte_cnt_3_s0</td>
</tr>
<tr>
<td>1.082</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C16[0][B]</td>
<td>controller/pls/O_byte_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.037</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.776, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.037, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.693</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.776</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.082</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/pls/psSEL_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>controller/pls/psSEL_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/W_scan_seq_pls:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sclk_5:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>R11C18[0][A]</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>1.776</td>
<td>1.776</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[1][A]</td>
<td style=" font-weight:bold;">controller/pls/psSEL_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sclk_5</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>35</td>
<td>R9C18[1][A]</td>
<td>sclk_s2/Q</td>
</tr>
<tr>
<td>1.037</td>
<td>1.037</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[1][A]</td>
<td>controller/pls/psSEL_s0/CLK</td>
</tr>
<tr>
<td>1.067</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>controller/pls/psSEL_s0</td>
</tr>
<tr>
<td>1.082</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C17[1][A]</td>
<td>controller/pls/psSEL_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.037</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.776, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.037, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C19[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R16C19[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C19[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n83_s0/I1</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R16C19[1][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n83_s0/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C19[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C19[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C19[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_inst/tx_inst/send_bit_cnt_0_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_inst/tx_inst/send_bit_cnt_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C8[0][A]</td>
<td>uart_inst/tx_inst/send_bit_cnt_0_s3/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R7C8[0][A]</td>
<td style=" font-weight:bold;">uart_inst/tx_inst/send_bit_cnt_0_s3/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C8[0][A]</td>
<td>uart_inst/tx_inst/n200_s3/I2</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C8[0][A]</td>
<td style=" background: #97FFFF;">uart_inst/tx_inst/n200_s3/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C8[0][A]</td>
<td style=" font-weight:bold;">uart_inst/tx_inst/send_bit_cnt_0_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C8[0][A]</td>
<td>uart_inst/tx_inst/send_bit_cnt_0_s3/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R7C8[0][A]</td>
<td>uart_inst/tx_inst/send_bit_cnt_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_inst/tx_inst/send_bit_cnt_3_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_inst/tx_inst/send_bit_cnt_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C16[1][A]</td>
<td>uart_inst/tx_inst/send_bit_cnt_3_s1/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R7C16[1][A]</td>
<td style=" font-weight:bold;">uart_inst/tx_inst/send_bit_cnt_3_s1/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C16[1][A]</td>
<td>uart_inst/tx_inst/n197_s1/I2</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C16[1][A]</td>
<td style=" background: #97FFFF;">uart_inst/tx_inst/n197_s1/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C16[1][A]</td>
<td style=" font-weight:bold;">uart_inst/tx_inst/send_bit_cnt_3_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C16[1][A]</td>
<td>uart_inst/tx_inst/send_bit_cnt_3_s1/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R7C16[1][A]</td>
<td>uart_inst/tx_inst/send_bit_cnt_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>axis_xpos_3_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>axis_xpos_3_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C8[1][A]</td>
<td>axis_xpos_3_s2/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R8C8[1][A]</td>
<td style=" font-weight:bold;">axis_xpos_3_s2/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C8[1][A]</td>
<td>n450_s9/I2</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R8C8[1][A]</td>
<td style=" background: #97FFFF;">n450_s9/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C8[1][A]</td>
<td style=" font-weight:bold;">axis_xpos_3_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C8[1][A]</td>
<td>axis_xpos_3_s2/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C8[1][A]</td>
<td>axis_xpos_3_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>axis_xpos_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>axis_xpos_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C7[1][A]</td>
<td>axis_xpos_0_s2/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R8C7[1][A]</td>
<td style=" font-weight:bold;">axis_xpos_0_s2/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C7[1][A]</td>
<td>n453_s12/I0</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R8C7[1][A]</td>
<td style=" background: #97FFFF;">n453_s12/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C7[1][A]</td>
<td style=" font-weight:bold;">axis_xpos_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C7[1][A]</td>
<td>axis_xpos_0_s2/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C7[1][A]</td>
<td>axis_xpos_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/svo_enc/vcursor_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/svo_enc/vcursor_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>svo_hdmi_inst/svo_enc/vcursor_13_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R7C31[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_enc/vcursor_13_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>svo_hdmi_inst/svo_enc/n80_s2/I3</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/svo_enc/n80_s2/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_enc/vcursor_13_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>svo_hdmi_inst/svo_enc/vcursor_13_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>svo_hdmi_inst/svo_enc/vcursor_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/svo_enc/hcursor_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/svo_enc/hcursor_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C30[1][A]</td>
<td>svo_hdmi_inst/svo_enc/hcursor_13_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R7C30[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_enc/hcursor_13_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C30[1][A]</td>
<td>svo_hdmi_inst/svo_enc/n109_s2/I3</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C30[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/svo_enc/n109_s2/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C30[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_enc/hcursor_13_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C30[1][A]</td>
<td>svo_hdmi_inst/svo_enc/hcursor_13_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R7C30[1][A]</td>
<td>svo_hdmi_inst/svo_enc/hcursor_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C20[0][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_1_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R16C20[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_term/p1_ypos_1_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C20[0][A]</td>
<td>svo_hdmi_inst/svo_term/n785_s2/I1</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R16C20[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/svo_term/n785_s2/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C20[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_term/p1_ypos_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C20[0][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_1_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C20[0][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C21[1][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_7_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R16C21[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_term/p1_ypos_7_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C21[1][A]</td>
<td>svo_hdmi_inst/svo_term/n779_s2/I3</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R16C21[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/svo_term/n779_s2/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C21[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_term/p1_ypos_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C21[1][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_7_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C21[1][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C22[0][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_11_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R16C22[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_term/p1_ypos_11_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C22[0][A]</td>
<td>svo_hdmi_inst/svo_term/n775_s4/I0</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R16C22[0][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/svo_term/n775_s4/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C22[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_term/p1_ypos_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C22[0][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_11_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C22[0][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C20[1][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_13_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R16C20[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_term/p1_ypos_13_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C20[1][A]</td>
<td>svo_hdmi_inst/svo_term/n773_s2/I3</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R16C20[1][A]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/svo_term/n773_s2/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C20[1][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/svo_term/p1_ypos_13_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C20[1][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_13_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C20[1][A]</td>
<td>svo_hdmi_inst/svo_term/p1_ypos_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.431</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>503.682</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>503.251</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>499.999</td>
<td>499.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>499.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>499.999</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>500.983</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>501.246</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>501.704</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>503.682</td>
<td>1.978</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>500.000</td>
<td>500.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>500.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>500.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>500.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>500.982</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>501.964</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>503.325</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C15[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK</td>
</tr>
<tr>
<td>503.295</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
<tr>
<td>503.251</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C15[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.078</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.978, 81.189%; tC2Q: 0.458, 18.811%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.964, 59.066%; route: 1.361, 40.934%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.431</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>503.682</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>503.251</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>499.999</td>
<td>499.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>499.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>499.999</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>500.983</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>501.246</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>501.704</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>503.682</td>
<td>1.978</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>500.000</td>
<td>500.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>500.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>500.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>500.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>500.982</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>501.964</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>503.325</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C15[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK</td>
</tr>
<tr>
<td>503.295</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0</td>
</tr>
<tr>
<td>503.251</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C15[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.078</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.978, 81.189%; tC2Q: 0.458, 18.811%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.964, 59.066%; route: 1.361, 40.934%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.398</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.277</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.675</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>2.838</td>
<td>1.807</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>3.464</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>5.277</td>
<td>1.813</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT41[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>3.968</td>
<td>3.968</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>3.968</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.629</td>
<td>1.661</td>
<td>tCL</td>
<td>FF</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>5.750</td>
<td>0.121</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]/FCLK</td>
</tr>
<tr>
<td>5.720</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
<tr>
<td>5.675</td>
<td>-0.045</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.210</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.968</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 13.305%; route: 3.621, 76.954%; tC2Q: 0.458, 9.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.121, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.398</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.277</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.675</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>2.838</td>
<td>1.807</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>3.464</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>5.277</td>
<td>1.813</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT39[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>3.968</td>
<td>3.968</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>3.968</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.629</td>
<td>1.661</td>
<td>tCL</td>
<td>FF</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>5.750</td>
<td>0.121</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]/FCLK</td>
</tr>
<tr>
<td>5.720</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
<tr>
<td>5.675</td>
<td>-0.045</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.210</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.968</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 13.305%; route: 3.621, 76.954%; tC2Q: 0.458, 9.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.121, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.398</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.277</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.675</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>2.838</td>
<td>1.807</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>3.464</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>5.277</td>
<td>1.813</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT38[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>3.968</td>
<td>3.968</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>3.968</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>5.629</td>
<td>1.661</td>
<td>tCL</td>
<td>FF</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>5.750</td>
<td>0.121</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]/FCLK</td>
</tr>
<tr>
<td>5.720</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
<tr>
<td>5.675</td>
<td>-0.045</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.210</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.968</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 13.305%; route: 3.621, 76.954%; tC2Q: 0.458, 9.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.121, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.565</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>502.686</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>503.251</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>499.999</td>
<td>499.999</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>499.999</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>499.999</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>500.983</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>501.246</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>501.704</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>502.686</td>
<td>0.982</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>500.000</td>
<td>500.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>500.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>500.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>500.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>500.982</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>501.964</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>503.325</td>
<td>1.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK</td>
</tr>
<tr>
<td>503.295</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0</td>
</tr>
<tr>
<td>503.251</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C15[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.078</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.001</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.982, 68.176%; tC2Q: 0.458, 31.824%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.964, 59.066%; route: 1.361, 40.934%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.360</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.277</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.637</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>2.838</td>
<td>1.807</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>3.464</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>5.277</td>
<td>1.813</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT41[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>7.936</td>
<td>7.936</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>7.936</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>9.597</td>
<td>1.661</td>
<td>tCL</td>
<td>RR</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>9.712</td>
<td>0.115</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]/FCLK</td>
</tr>
<tr>
<td>9.682</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
<tr>
<td>9.637</td>
<td>-0.045</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.203</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>7.936</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 13.305%; route: 3.621, 76.954%; tC2Q: 0.458, 9.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.115, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.360</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.277</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.637</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>2.838</td>
<td>1.807</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>3.464</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>5.277</td>
<td>1.813</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT39[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>7.936</td>
<td>7.936</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>7.936</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>9.597</td>
<td>1.661</td>
<td>tCL</td>
<td>RR</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>9.712</td>
<td>0.115</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]/FCLK</td>
</tr>
<tr>
<td>9.682</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
<tr>
<td>9.637</td>
<td>-0.045</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.203</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>7.936</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 13.305%; route: 3.621, 76.954%; tC2Q: 0.458, 9.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.115, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.360</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.277</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.637</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>2.838</td>
<td>1.807</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>3.464</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>5.277</td>
<td>1.813</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT38[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>7.936</td>
<td>7.936</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>7.936</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>9.597</td>
<td>1.661</td>
<td>tCL</td>
<td>RR</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>9.712</td>
<td>0.115</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]/FCLK</td>
</tr>
<tr>
<td>9.682</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
<tr>
<td>9.637</td>
<td>-0.045</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.203</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>7.936</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 13.305%; route: 3.621, 76.954%; tC2Q: 0.458, 9.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.115, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.268</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>24.952</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>24.952</td>
<td>4.728</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOR17[A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 4.728, 91.163%; tC2Q: 0.458, 8.837%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>14.736</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>23.483</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>23.483</td>
<td>3.260</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C14[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C14[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.260, 87.674%; tC2Q: 0.458, 12.326%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.211</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>23.008</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>23.008</td>
<td>2.785</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C14[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C14[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C14[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.785, 85.870%; tC2Q: 0.458, 14.130%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.211</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>23.008</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>23.008</td>
<td>2.785</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C14[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C14[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C14[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.785, 85.870%; tC2Q: 0.458, 14.130%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.211</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>23.008</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>23.008</td>
<td>2.785</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C14[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C14[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C14[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.785, 85.870%; tC2Q: 0.458, 14.130%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.041</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>22.179</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>22.179</td>
<td>1.956</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C14[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C14[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C14[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.956, 81.013%; tC2Q: 0.458, 18.987%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.838</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.382</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>21.382</td>
<td>1.158</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C18[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C18[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.158, 71.649%; tC2Q: 0.458, 28.351%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.838</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.382</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>21.382</td>
<td>1.158</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C18[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C18[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R16C18[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.158, 71.649%; tC2Q: 0.458, 28.351%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.838</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.382</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>21.382</td>
<td>1.158</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C18[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C18[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C18[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.158, 71.649%; tC2Q: 0.458, 28.351%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.838</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.382</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>21.382</td>
<td>1.158</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C18[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C18[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.158, 71.649%; tC2Q: 0.458, 28.351%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.838</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.382</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>21.382</td>
<td>1.158</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C17[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C17[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C17[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.158, 71.649%; tC2Q: 0.458, 28.351%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.838</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.382</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>21.382</td>
<td>1.158</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C17[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C17[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C17[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.158, 71.649%; tC2Q: 0.458, 28.351%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.838</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.382</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>38.219</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.502</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.765</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>20.223</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>21.382</td>
<td>1.158</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C19[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>37.037</td>
<td>37.037</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>37.037</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>38.019</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>38.263</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C19[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK</td>
</tr>
<tr>
<td>38.219</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C19[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>18.519</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 78.948%; route: 0.262, 21.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.158, 71.649%; tC2Q: 0.458, 28.351%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>34.932</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.277</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.210</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>2.838</td>
<td>1.807</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>3.464</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>5.277</td>
<td>1.813</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT41[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.682</td>
<td>39.682</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.682</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]/PCLK</td>
</tr>
<tr>
<td>40.210</td>
<td>-0.045</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.682</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 13.305%; route: 3.621, 76.954%; tC2Q: 0.458, 9.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>34.932</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.277</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.210</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>2.838</td>
<td>1.807</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>3.464</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>5.277</td>
<td>1.813</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT39[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.682</td>
<td>39.682</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.682</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]/PCLK</td>
</tr>
<tr>
<td>40.210</td>
<td>-0.045</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.682</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 13.305%; route: 3.621, 76.954%; tC2Q: 0.458, 9.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>34.932</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.277</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.210</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>2.838</td>
<td>1.807</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>3.464</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>5.277</td>
<td>1.813</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT38[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.682</td>
<td>39.682</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.682</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]/PCLK</td>
</tr>
<tr>
<td>40.210</td>
<td>-0.045</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.682</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 13.305%; route: 3.621, 76.954%; tC2Q: 0.458, 9.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.059</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1353.759</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1352.700</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1351.850</td>
<td>1351.850</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1351.850</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1351.850</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1352.697</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1352.892</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>1353.226</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>1353.759</td>
<td>0.534</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1350.000</td>
<td>1350.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1350.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>1350.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>1350.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>1350.844</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1351.689</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>1352.655</td>
<td>0.966</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK</td>
</tr>
<tr>
<td>1352.685</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0</td>
</tr>
<tr>
<td>1352.700</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C15[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.612</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-1.850</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.534, 61.551%; tC2Q: 0.333, 38.449%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.689, 63.613%; route: 0.966, 36.387%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.559</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.349</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.790</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>1.683</td>
<td>0.836</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>2.068</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>3.349</td>
<td>1.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT41[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.661</td>
<td>1.661</td>
<td>tCL</td>
<td>RR</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.745</td>
<td>0.085</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]/FCLK</td>
</tr>
<tr>
<td>1.775</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
<tr>
<td>1.790</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.232</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.385, 13.577%; route: 2.117, 74.667%; tC2Q: 0.333, 11.755%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.085, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.559</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.349</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.790</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>1.683</td>
<td>0.836</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>2.068</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>3.349</td>
<td>1.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT39[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.661</td>
<td>1.661</td>
<td>tCL</td>
<td>RR</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.745</td>
<td>0.085</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]/FCLK</td>
</tr>
<tr>
<td>1.775</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
<tr>
<td>1.790</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.232</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.385, 13.577%; route: 2.117, 74.667%; tC2Q: 0.333, 11.755%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.085, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.559</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.349</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.790</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>1.683</td>
<td>0.836</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>2.068</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>3.349</td>
<td>1.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT38[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.661</td>
<td>1.661</td>
<td>tCL</td>
<td>RR</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.745</td>
<td>0.085</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]/FCLK</td>
</tr>
<tr>
<td>1.775</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
<tr>
<td>1.790</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.232</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.385, 13.577%; route: 2.117, 74.667%; tC2Q: 0.333, 11.755%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.085, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.684</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1354.384</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1352.700</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1351.850</td>
<td>1351.850</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1351.850</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1351.850</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1352.697</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1352.892</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>1353.226</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>1354.384</td>
<td>1.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C15[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1350.000</td>
<td>1350.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1350.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>1350.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>1350.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>1350.844</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1351.689</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>1352.655</td>
<td>0.966</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C15[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK</td>
</tr>
<tr>
<td>1352.685</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
<tr>
<td>1352.700</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C15[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.612</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-1.850</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.159, 77.657%; tC2Q: 0.333, 22.343%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.689, 63.613%; route: 0.966, 36.387%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.684</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1354.384</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1352.700</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1351.850</td>
<td>1351.850</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1351.850</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>1351.850</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>1352.697</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1352.892</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>1353.226</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>1354.384</td>
<td>1.159</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C15[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1350.000</td>
<td>1350.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1350.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>1350.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>1350.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOL11[B]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>1350.844</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1351.689</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>1352.655</td>
<td>0.966</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C15[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK</td>
</tr>
<tr>
<td>1352.685</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0</td>
</tr>
<tr>
<td>1352.700</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C15[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.612</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-1.850</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.159, 77.657%; tC2Q: 0.333, 22.343%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.689, 63.613%; route: 0.966, 36.387%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.821</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.349</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>1.683</td>
<td>0.836</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>2.068</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>3.349</td>
<td>1.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT41[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]/PCLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.385, 13.577%; route: 2.117, 74.667%; tC2Q: 0.333, 11.755%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.821</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.349</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>1.683</td>
<td>0.836</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>2.068</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>3.349</td>
<td>1.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT39[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]/PCLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.385, 13.577%; route: 2.117, 74.667%; tC2Q: 0.333, 11.755%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.821</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.349</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>1.683</td>
<td>0.836</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>2.068</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>3.349</td>
<td>1.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT38[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]/PCLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.385, 13.577%; route: 2.117, 74.667%; tC2Q: 0.333, 11.755%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.521</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.349</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>-2.172</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>1.683</td>
<td>0.836</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>2.068</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>3.349</td>
<td>1.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT41[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[0]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>-3.968</td>
<td>-3.968</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>-3.968</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>-2.308</td>
<td>1.661</td>
<td>tCL</td>
<td>FF</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>-2.217</td>
<td>0.090</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]/FCLK</td>
</tr>
<tr>
<td>-2.187</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
<tr>
<td>-2.172</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT41[A]</td>
<td>svo_hdmi_inst/tmds_serdes[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.238</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-3.968</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.385, 13.577%; route: 2.117, 74.667%; tC2Q: 0.333, 11.755%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.090, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.521</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.349</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>-2.172</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>1.683</td>
<td>0.836</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>2.068</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>3.349</td>
<td>1.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT39[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[1]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>-3.968</td>
<td>-3.968</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>-3.968</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>-2.308</td>
<td>1.661</td>
<td>tCL</td>
<td>FF</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>-2.217</td>
<td>0.090</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]/FCLK</td>
</tr>
<tr>
<td>-2.187</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
<tr>
<td>-2.172</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT39[A]</td>
<td>svo_hdmi_inst/tmds_serdes[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.238</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-3.968</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.385, 13.577%; route: 2.117, 74.667%; tC2Q: 0.333, 11.755%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.090, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.521</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.349</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>-2.172</td>
</tr>
<tr>
<td class="label">From</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>593</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C28[0][A]</td>
<td>svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R15C28[0][A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q</td>
</tr>
<tr>
<td>1.683</td>
<td>0.836</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C25[1][B]</td>
<td>svo_hdmi_inst/n142_s1/I1</td>
</tr>
<tr>
<td>2.068</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>113</td>
<td>R11C25[1][B]</td>
<td style=" background: #97FFFF;">svo_hdmi_inst/n142_s1/F</td>
</tr>
<tr>
<td>3.349</td>
<td>1.281</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT38[A]</td>
<td style=" font-weight:bold;">svo_hdmi_inst/tmds_serdes[2]/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>-3.968</td>
<td>-3.968</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>-3.968</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>-2.308</td>
<td>1.661</td>
<td>tCL</td>
<td>FF</td>
<td>4</td>
<td>PLL_R</td>
<td>u_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>-2.217</td>
<td>0.090</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]/FCLK</td>
</tr>
<tr>
<td>-2.187</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
<tr>
<td>-2.172</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT38[A]</td>
<td>svo_hdmi_inst/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.238</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-3.968</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.385, 13.577%; route: 2.117, 74.667%; tC2Q: 0.333, 11.755%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.090, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.119</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.163</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.163</td>
<td>0.270</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C17[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C17[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C17[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.270, 44.739%; tC2Q: 0.333, 55.261%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.119</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.163</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.163</td>
<td>0.270</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C17[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C17[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C17[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.270, 44.739%; tC2Q: 0.333, 55.261%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.123</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.167</td>
<td>0.274</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C18[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C18[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C18[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.274, 45.080%; tC2Q: 0.333, 54.920%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.123</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.167</td>
<td>0.274</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C18[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C18[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C18[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.274, 45.080%; tC2Q: 0.333, 54.920%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.123</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.167</td>
<td>0.274</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C18[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C18[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C18[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.274, 45.080%; tC2Q: 0.333, 54.920%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.123</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.167</td>
<td>0.274</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C18[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C18[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C18[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.274, 45.080%; tC2Q: 0.333, 54.920%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.123</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.167</td>
<td>0.274</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C18[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C18[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C18[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.274, 45.080%; tC2Q: 0.333, 54.920%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.367</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.411</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.411</td>
<td>0.517</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C19[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C19[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C19[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.517, 60.823%; tC2Q: 0.333, 39.177%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.367</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.411</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.411</td>
<td>0.517</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C19[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C19[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C19[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.517, 60.823%; tC2Q: 0.333, 39.177%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.367</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.411</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.411</td>
<td>0.517</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C19[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C19[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C19[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.517, 60.823%; tC2Q: 0.333, 39.177%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.367</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.411</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.411</td>
<td>0.517</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.517, 60.823%; tC2Q: 0.333, 39.177%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.367</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.411</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/triger_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.411</td>
<td>0.517</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C19[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/triger_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C19[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C19[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.517, 60.823%; tC2Q: 0.333, 39.177%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>19.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.435</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_osc:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_osc:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>18.518</td>
<td>18.518</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>18.518</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>19.365</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>19.560</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>19.894</td>
<td>0.333</td>
<td>tC2Q</td>
<td>FR</td>
<td>58</td>
<td>R21C19[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>20.435</td>
<td>0.541</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C18[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_osc</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>133</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C18[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C18[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.013</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-18.518</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.847, 81.254%; route: 0.195, 18.746%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.541, 61.881%; tC2Q: 0.333, 38.119%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.399</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.649</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/W_rxd_mask_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>13.127</td>
<td>3.127</td>
<td>tNET</td>
<td>FF</td>
<td>controller/W_rxd_mask_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>21.776</td>
<td>1.776</td>
<td>tNET</td>
<td>RR</td>
<td>controller/W_rxd_mask_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.623</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.873</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/cmd/pad_id_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>12.376</td>
<td>2.376</td>
<td>tNET</td>
<td>FF</td>
<td>controller/cmd/pad_id_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>21.249</td>
<td>1.249</td>
<td>tNET</td>
<td>RR</td>
<td>controller/cmd/pad_id_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.623</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.873</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/cmd/conf_done_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>12.376</td>
<td>2.376</td>
<td>tNET</td>
<td>FF</td>
<td>controller/cmd/conf_done_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>21.249</td>
<td>1.249</td>
<td>tNET</td>
<td>RR</td>
<td>controller/cmd/conf_done_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.623</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.873</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/cmd/O_TXD_DAT_7_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>12.376</td>
<td>2.376</td>
<td>tNET</td>
<td>FF</td>
<td>controller/cmd/O_TXD_DAT_7_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>21.249</td>
<td>1.249</td>
<td>tNET</td>
<td>RR</td>
<td>controller/cmd/O_TXD_DAT_7_s1/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.623</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.873</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/cmd/O_TXD_DAT_6_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>12.376</td>
<td>2.376</td>
<td>tNET</td>
<td>FF</td>
<td>controller/cmd/O_TXD_DAT_6_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>21.249</td>
<td>1.249</td>
<td>tNET</td>
<td>RR</td>
<td>controller/cmd/O_TXD_DAT_6_s1/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.623</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.873</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/cmd/O_TXD_DAT_4_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>12.376</td>
<td>2.376</td>
<td>tNET</td>
<td>FF</td>
<td>controller/cmd/O_TXD_DAT_4_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>21.249</td>
<td>1.249</td>
<td>tNET</td>
<td>RR</td>
<td>controller/cmd/O_TXD_DAT_4_s1/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.623</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.873</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/cmd/O_TXD_DAT_1_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>12.376</td>
<td>2.376</td>
<td>tNET</td>
<td>FF</td>
<td>controller/cmd/O_TXD_DAT_1_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>21.249</td>
<td>1.249</td>
<td>tNET</td>
<td>RR</td>
<td>controller/cmd/O_TXD_DAT_1_s1/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.623</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.873</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/cmd/conf_state_2_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>12.376</td>
<td>2.376</td>
<td>tNET</td>
<td>FF</td>
<td>controller/cmd/conf_state_2_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>21.249</td>
<td>1.249</td>
<td>tNET</td>
<td>RR</td>
<td>controller/cmd/conf_state_2_s1/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.623</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.873</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/cmd/conf_state_0_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>12.376</td>
<td>2.376</td>
<td>tNET</td>
<td>FF</td>
<td>controller/cmd/conf_state_0_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>21.249</td>
<td>1.249</td>
<td>tNET</td>
<td>RR</td>
<td>controller/cmd/conf_state_0_s1/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.623</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.873</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/cmd/conf_state_1_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>12.376</td>
<td>2.376</td>
<td>tNET</td>
<td>FF</td>
<td>controller/cmd/conf_state_1_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_TXSET</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/W_TXSET_s/F</td>
</tr>
<tr>
<td>21.249</td>
<td>1.249</td>
<td>tNET</td>
<td>RR</td>
<td>controller/cmd/conf_state_1_s1/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>593</td>
<td>clk_p</td>
<td>0.398</td>
<td>0.659</td>
</tr>
<tr>
<td>206</td>
<td>control0[0]</td>
<td>-8.000</td>
<td>1.726</td>
</tr>
<tr>
<td>133</td>
<td>clk_d</td>
<td>-4.283</td>
<td>0.262</td>
</tr>
<tr>
<td>113</td>
<td>n142_5</td>
<td>0.398</td>
<td>2.298</td>
</tr>
<tr>
<td>84</td>
<td>pixel_fifo_rdaddr[2]</td>
<td>26.933</td>
<td>2.830</td>
</tr>
<tr>
<td>60</td>
<td>n7796_6</td>
<td>32.975</td>
<td>3.413</td>
</tr>
<tr>
<td>60</td>
<td>n169_7</td>
<td>35.286</td>
<td>1.821</td>
</tr>
<tr>
<td>60</td>
<td>n169_5</td>
<td>32.553</td>
<td>1.357</td>
</tr>
<tr>
<td>58</td>
<td>rst_ao</td>
<td>-0.431</td>
<td>4.728</td>
</tr>
<tr>
<td>45</td>
<td>pixel_fifo_rdaddr[1]</td>
<td>26.396</td>
<td>3.461</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R15C13</td>
<td>88.89%</td>
</tr>
<tr>
<td>R8C21</td>
<td>87.50%</td>
</tr>
<tr>
<td>R16C15</td>
<td>86.11%</td>
</tr>
<tr>
<td>R16C22</td>
<td>86.11%</td>
</tr>
<tr>
<td>R12C17</td>
<td>86.11%</td>
</tr>
<tr>
<td>R14C14</td>
<td>86.11%</td>
</tr>
<tr>
<td>R16C18</td>
<td>83.33%</td>
</tr>
<tr>
<td>R12C25</td>
<td>83.33%</td>
</tr>
<tr>
<td>R21C29</td>
<td>83.33%</td>
</tr>
<tr>
<td>R12C8</td>
<td>81.94%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name clk_osc -period 37.037 -waveform {0 18.518} [get_ports {clk}]</td>
</tr>
</table>
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